Thank you so much! My Uni barely goes over verilog, yet all our labs uses it. They really should have a separate class for this, but instead they teach us c++
@Deltax0428
3 ай бұрын
Rather than using if else for 4to1 mux can we use case statement ?
@danielarama9328
Жыл бұрын
WHY NOT ?? module Mux_n_1Bit #(parameter n=8)( input [n-1:0] Data_in, input [$clog2(n)-1:0] sel, output reg f ); integer i; always @(Data_in, sel) begin f = Data_in[sel]; end endmodule
Пікірлер: 3