J K flip flop behaves just like R S flip flop. The Q and Q' outputs will only change state on the falling edge of the clock signal. When both J and K values are 0 , there is no change in the outputs Q and Q'. When both J and K are held at 1, the circuit will oscillate rapidly called as toggling state. When J is 0 and K is 1, Q is 0 and Q' is 1. When J is 1 and K is 0, Q is 1 and Q' is 0.
Негізгі бет ADE Lab sessions| Experiment No. 6 a) J K Flip Flop
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