Abstract:
"The CMOS fabrication process suffers from variations within the different manufacturing steps. These variations directly influence CMOS device parameters such as threshold voltage or mobility. Therefore, performance parameters of analog circuits are varying as well. An analog designer faces two challenges: First, one must design a circuit to be robust against such variations. Second, robustness needs verification by simulation to ensure high yield in production. This talk gives a quick overview on the typical variations within the CMOS fabrication process and some design hints to make circuits robust. The main part will show verification methods in the statistical domain which reach far beyond the commonly used and well-known Monte Carlo technique. There will be a short overview on commercial tools, which implement these statistical methods."
This presentation was recorded as part of the lecture "Selected Topics of Advanced Analog Chip Design" from the Institute of Electronics at TU Graz.
Special thanks to Dr. Stefan Gansinger, for the insightful presentation.
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