Fungible DFT: from Chiplets to Chip
Adam Cron
Synopsys
The maturity of Design-for-Test (DFT) technology, in general, comes into better focus when your multi-die package has chips, or chiplets, of all kinds scattered around the substrate: memories, digital cores, communications ports, etc. All require different test, diagnostic, and repair solutions, but all these solutions are well in hand - and most are mature. The difference, today, is that they are applied not to a 2D physical space, but to a virtual 3D physical layout. This presentation will start at the lower-levels of implementation and move up the hierarchy showing how current DFT, diagnostic, and repair technologies as well as standards can be applied to a chiplet-based, multi-die package to enable manufacturing and field scenarios. It will show how DFT structures such as scan and compression can be hooked together with 3rd-party IP DFT, memory BIST, logic BIST, and die-to-die connectivity testing structures, and accessed using standards such as IEEE 1838, 1500, and 1687; and then be further connected to a functional high-speed interface, if required.
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