#digitaldesign #logicdesign #verilog
This video covers complete Digital Logic Design course. Intended audience is lazy students who want to cover everything last night before exam, people who want to revise stuff for qualifiers or interviews in short time and self paced learners who do not have time to watch complete 16 weeks course.
First 2.5 hrs cover most of the content generally taught in Digital Logic Design courses. Next 2 hrs cover Verilog and various design examples that might be useful for advanced audience.
Slides can be downloaded at
tinyurl.com/dld-slides
Jump to relevant sections by clicking time tag below:
(0:00) Number Systems (conversions, 2's complement form)
(28:06) Boolean Algebra and logic gates (SOP, POS, Demorgan's law)
(53:30) Gate level minimizations (Kmaps)
(1:27:07) Combinational Circuits (Decoder, Encoder, Priority Encoder, Mux, Demux, Comparator, Adder/Subtractor, Multiplier)
(1:54:40) Sequential circuit design (Latches, Flipflops, State machines)
(2:28:48) Sequential circuit analysis
(2:39:07) Verilog for synthesis
(3:25:21) Verilog for simulation
(3:53:28) Design examples review (level to pulse, digital clock, BRAMs, VGA)
(4:02:46) Processor design example
Негізгі бет Digtal Logic Design crash course in 4 hrs [Urdu/Hindi]
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