Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This will reduce time spent validating designs. SystemVerilog Assertions (SVA), an assertion sub-language of the IEEE Std 1800-2005 SystemVerilog. It is used to specify assertions and functional coverage properties for validating concurrent systems. This video is intended to describe types of FVs and their suitability. The position in the elaborated modern VLSI Design flow are justified in the presence of Dynamic Simulation. SVA assertion concepts are introduced and their immediate uses are demonstrated.
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Dynamic Simulation vs Formal Verification (and Assertions):
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