The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.
@hywu809
10 ай бұрын
就是芯片厂家自定的business term , 而且各家还不统一,三星最水,台积电次之,intel最老实。 如果按芯片里的晶体管密度算,这些term可能还有一些道理, Finfet/GAA, 所谓立体场效应,平面缩小受到一些限制,那就往立体场效应方向发展。
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