A quick note! In the python test code, I didn't test between 1) discontinuities on the packet boundaries, and 2) discontinuities in the packets themselves. I've modified my python test code (in github here: github.com/HDLForBeginners/Examples/blob/main/eth_counter_improved/py/receive.py ) to take this into account. This does confirm that even though packets are dropped, the remaining ones are kept in-tact. Once again, thanks for watching :)
@vioreltanase186
Жыл бұрын
Hey , thank you so much for your content, I appreciate what you do and how you explain everything , keep doing ! I need to do for my bachelor's thesis a communication between an fpga and my laptop but when I generate the frames (after programming the fpga ) my fcs is just a sample of incrementing data and not the one from buffer...I don't know why, but in simulation it appears .. I have some screenshots in wireshark and simulation if you can help me .. please .
@yapet
2 жыл бұрын
Always wanted to learn verilog and circuits stuff. Such a wonderful presentation, clear explanation, straight-to-the-point editing. What a wholesome vid
@benguan9477
2 жыл бұрын
this channel is awesome! thanks for the amazing content!
@AustinTronics
2 жыл бұрын
This is awesome! Very practical content. Thank you!
@slicer95
2 жыл бұрын
Thanks a lot for these videos!
@zwykyziomek2570
2 жыл бұрын
channel: " FPGAs for Beginners" video: "Handling Ethernet FIFO overflows in SystemVerilog" love that lmao 😂
@FPGAsforBeginners
2 жыл бұрын
I know, right!
@venkateshiyer5073
2 жыл бұрын
great video. Thanks for posting. On a serious note, how do I learn sync and async fifo coding in verilog/SV. I have only recently started as a verification engineer. Any inputs is welcome. Thanks in advance!
@georgeyu9898
2 жыл бұрын
Look up Cliff Cummings's whitepapers. They're very good.
@venkateshiyer5073
2 жыл бұрын
@@georgeyu9898 sure I will. Thanks
@beartb4253
Жыл бұрын
Hi could you make a video show us how you set up the connection between FPGA and Ethernet on your computer? Thank you so much
@FPGAsforBeginners
Жыл бұрын
I think I show that in a video somewhere? I think one of my ethernet videos.
@toomaray2172
2 жыл бұрын
hello, how do you simulate 2d arrays in systemverilog? i am trying to work on a project which is doing an efficient serial design for digital image processing filters (kernels), basically my cell takes an input like this : input logic [7:0]a[5][5]; for a 5x5 matrix with each element 8 bits, how do you simulate such thing? do you have test bench examples?
@FPGAsforBeginners
2 жыл бұрын
I recommend keeping all your dimensions on the left of the signal name: logic [7:0][5:0][5:0] a; You can slice them any way you want that way, and you index the same way you define, eg: logic [a][b][c] a; assign a[a][b][c] = 1 assign a[a][b] = 10 and you can assign all zeros assign a = '0 Much more flexible when the dimensions are on the left of the name. But it is only compatible in systemverilog.
@aaronlinell3916
2 жыл бұрын
Will you discuss memory mapped infrastructure? (ie interconnects / translators / arbitration)
@FPGAsforBeginners
2 жыл бұрын
Eventually, yes. AXI is on my list of to-do, although it's going to take a while because it takes a lot of prep work to create those videos in particular.
@juanmacias5922
2 жыл бұрын
Weird question, what language is that you are coding in? Kind of looked like Java, until I saw "end" instead of semicolons.
@ryanvoots9827
2 жыл бұрын
Based on the rest of her videos, Verilog. Another option for FPGAs and such is VHDL
@juanmacias5922
2 жыл бұрын
@@ryanvoots9827 Hey, thanks!
@harleyarmstrong5947
2 жыл бұрын
I believe its system Verilog, plain old Verilog you would not use the logic type, instead you would use reg and wire.
@FPGAsforBeginners
2 жыл бұрын
Yup it's SystemVerilog! I'll add that to the title :). Thanks!
@AdityagoelK_EC-
2 жыл бұрын
I'm starting as a verification engineer soon, can give me some sources to learn system verilog. Thanks in advance!
@FPGAsforBeginners
2 жыл бұрын
(System)Verilog: learning.edx.org/course/course-v1:LinuxFoundationX+LFD111x+1T2021/home chipdev.io/ hdlbits.01xz.net/wiki/Main_Page makerchip.com/sandbox/ classweb.ece.umd.edu/enee359a/verilog_tutorial.pdf Here ya go, all free!
@dirasadirasa2499
2 жыл бұрын
I don't why i am here 😭
@FPGAsforBeginners
2 жыл бұрын
I don't know either but I'm glad to have you :)
@aumel8752
2 жыл бұрын
@@FPGAsforBeginners Paid advertisement :D jk I really enjoyed content in this video
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