nice bro u came back you explaining the concepts very clearly bro.
@KarthikVippala
4 жыл бұрын
Thank you brother 👊
@danny_racho
Жыл бұрын
Hey, you used one input more than needed for P1' at 2:46 You can simplify it from (P1' = ~P1 & P0) to (P1' = P0). But great video and very well structured. Thanks :)
@prabhakarreddy9729
3 жыл бұрын
Hi Karthik ,as per my knowledge one hot coding also recommend in asic because for debugging it is very easy while when we get timing violation
@KarthikVippala
3 жыл бұрын
Yes prabhakar , we also use one hot in asic but it suits better for FPGA. Good luck, good health 👍
@ScalarFactory
2 жыл бұрын
Really thanks. Your explanation was so helpful.
@KarthikVippala
2 жыл бұрын
Namaste 🙏 capital , thanks for the support, good luck and great health 👍😊
@niharikaj6320
2 жыл бұрын
yes why is eco consideration needed
@lakshyabhardwaj9541
3 жыл бұрын
What is ECO?
@KarthikVippala
3 жыл бұрын
Namaskaram 🙏 Lakshya, Engineering change order , ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC logic synthesis, technology mapping, place ,route, extraction and timing verification. EDA tools are often built with incremental modes of operation to facilitate this type of ECO. Good luck & great health 👍😊
@yutinggan1679
4 жыл бұрын
could you pls explain a bit more about the timing path. There are thousands of questions about set up/hold on time violation.
@KarthikVippala
4 жыл бұрын
Hey Yuting Gan , please check my videos on setup time and hold time video , In future I willl make them Thanks for asking , good luck, good health 👍
@yutinggan1679
4 жыл бұрын
The way you lecture and the voice you speak are really like my professor at Southampton University. Maybe they can offer you a job there :D
@KarthikVippala
4 жыл бұрын
😄 , thanks for the other kind words , Can you be specific about the topic so that I can make a video for you 👍
@yutinggan1679
4 жыл бұрын
@@KarthikVippala I am really flattered to be treated like this. Just do the video as you want, thank you!
@KarthikVippala
4 жыл бұрын
@@yutinggan1679 your welcome 👍
@bhavanas7914
2 жыл бұрын
thank you so muchhhhhhh 🙏🙏🙏
@VarunsSharma1901
3 жыл бұрын
How to do one hot encoding in verilog?
@KarthikVippala
3 жыл бұрын
Namaste 🙏 varun , instead of using 0,1,2.. for states we can replace them with 1,2,4,8... In one hot. Thanks for asking, good luck and great health 👍😊
@omganeshchoas9097
4 жыл бұрын
Put video on fsm overlap and non overlap detaily with cirucuits connection bro
@KarthikVippala
4 жыл бұрын
Ganesh , do you mean for sequence detectors or any FSM
@omganeshchoas9097
4 жыл бұрын
@@KarthikVippala Both bro I am not have that much idea bro on both
@KarthikVippala
4 жыл бұрын
@@omganeshchoas9097 ok I will make one 👍
@ranjanparnami
3 жыл бұрын
Thankyou
@KarthikVippala
3 жыл бұрын
Your welcome , thanks for watching so many videos 🙏
@uday5786
4 жыл бұрын
what is eco?
@KarthikVippala
4 жыл бұрын
Engineering change order , ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC logic synthesis, technology mapping, place ,route, extraction and timing verification. EDA tools are often built with incremental modes of operation to facilitate this type of ECO.
@uday5786
4 жыл бұрын
hey karthik ...thanks for the video..i request you to make a video on latch up problem in mosfets
@KarthikVippala
4 жыл бұрын
Ok uday I will do it , but I need some time for it 👍
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