Alexander Conklin,
Head of Hardware Engineering, Rain AI
The compute intensive demands of AI workloads have given rise to a new era in accelerator design. In this talk we’ll take a look at how Rain AI used Andes AX45MPV and, more specifically custom vector instructions, in the design of a low power in-memory compute architecture. Attendees will gain insights into how Andes Custom Vector Extension can be used to generate a set of rich instructions, encapsulating the most important AI operands. The speaker will walk through real examples of instructions used by Rain to program ultra-efficient in-memory compute blocks and non-linear operator accelerators. Central to the discussion is commentary on the benefits in flexibility and software programmability brought forth by this approach to architecture and ISA design.
Негізгі бет RISC-V Con 2024: "Leveraging RISC-V for hardware software co-design of low power AI accelerators"
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