This is one of the best guides I've ever seen, thank you so much! I don't know if I would've been able to figure out how to do branch statements without your diagram.
@JohnsBasement
Жыл бұрын
You and me both! It wasn't until I found myself sketching them out by hand that I realized a) how they work and b) that I am likely not alone and that releasing even a 1/2 finished document with them in it would be a good thing. Thank you for your such kind words!
@mikafoxx2717
6 ай бұрын
This is reavealing why RISC-V is such a good instruction set. Fixed rotates, simple non moving bits.. you can almost negate any real microcode, just straight up combinational logic on a few bits. Give a few fixed shift offset wires, wire up register select to the instruction.. it's genius. Even a 5602 is complicated compared to the decoding of these in silicon.
@JohnsBasement
6 ай бұрын
Yeah, They did a pretty good job with RISC-V! I hope to do more with it at some point. The base ISA is simple enough to try a stab at some FPGA implementations.
@Tapajara
3 ай бұрын
This is the best RISC-V video that I have seen. I reproduced your table in a ϕText document.
@JohnsBasement
3 ай бұрын
Thank you. Glad you liked it!
@ChronicoOne
5 ай бұрын
It's amazing how well you describe all of the technical details and still keep my attention. Great video! I had an idea to try to write an RV32I emulator in CPP and compile it to run on itself. Seems practical after watching this video!
@JohnsBasement
5 ай бұрын
Thanks! If you are looking for ideas, here is a 3-part assignment I gave my students a while back on writing their own: github.com/Architecture-And-Organization/Memory-Simulator/releases/download/2022-fall/handout.pdf github.com/Architecture-And-Organization/RV32I-Disassembler/releases/download/2022-fall/handout.pdf github.com/Architecture-And-Organization/RV32I-Simulator/releases/download/2022-fall/handout.pdf There are also some videos in the course lectures where I show them how to add a thin layer to this design so that it can run multiple cores (See the course web site in the video description.)
@ChronicoOne
5 ай бұрын
@@JohnsBasement Wow thanks! I will definitely take a look at that
@averagestudent1158
4 ай бұрын
Thank you for the video sir, this has been incredibly helpful in making my own riscv processor. Also the instruction set made coding it much easier.
@JohnsBasement
4 ай бұрын
Glad to know it helped!
@bluebirdgoneaway
Жыл бұрын
Great lecture! You're so good at simplifying and clarifying concepts, John! In addition, John Lithgow-like voice sounds so clear.
@JohnsBasement
Жыл бұрын
Thanks!
@davidgussler1438
2 жыл бұрын
Great video! Helped me understand the funky immediate business going on with B and J type instructions
@JohnsBasement
2 жыл бұрын
Thanks! It turns out that understanding the rationale for the format of the immediate operands is what drove me to consolidate and post my notes on related assembly language topics and draw the 'ribbon' pictures that illustrate the untangling of the immediate bits.
@davidgussler1438
2 жыл бұрын
@@JohnsBasement Really enjoying your RISC-V series. I wish my professors in college were as clear as you. Thanks for making your videos public. Surprised your channel hasn’t gotten more traction by now!
@suncrafterspielt9479
3 жыл бұрын
Thanks for the very well explained pdf and video
@shawnarmstrong3339
3 жыл бұрын
Beautifully explained.
@JohnsBasement
3 жыл бұрын
Thank you for such kind words!
@vadimshatov9935
Жыл бұрын
It took me time to understand that I do not need to calculate the offset relative to the address myself(for B-type instructions). The compiler will do it for me. Maybe I didn't listen carefully :( Thank you very much for this playlist!
@JohnsBasement
Жыл бұрын
Sorry 'bout that. 😕. This lecture assumes a familiarity with assemblers, labels and so on.
@caglararaz
2 жыл бұрын
Thank you very much. Well explained. I understand the subject way better now.
@JohnsBasement
2 жыл бұрын
Glad to hear that!
@erascarecrow2541
Жыл бұрын
When extracting the function/data from the instructions (for the disassembler ~14:00), i would shift first and then AND. f3 = (I & 0x00007000) >> 7; vs f3 = (I >> 7) & 0x7;
@JohnsBasement
Жыл бұрын
Any particular reason?
@samuelcastro294
3 жыл бұрын
Amazing video!
@JohnsBasement
3 жыл бұрын
Thanks!
@mohankrishnapeddi4109
11 ай бұрын
ths is thoe one of the bet guidance . sir I am requesting you to send me the pdf of this book sir please
@JohnsBasement
11 ай бұрын
See the link to it in the video description. There are PDF under a tab called Releases.
@hossamfadeel
3 жыл бұрын
Thanks a lot.
@ratodesgracadaomiguitau8758
Жыл бұрын
thank you.
@JohnsBasement
Жыл бұрын
You are welcome.
@user-xn3ym4cr6h
2 жыл бұрын
well informative
@JohnsBasement
2 жыл бұрын
Thanks!
@codyerpelding3166
3 жыл бұрын
It probably doesn't really matter but it seems like the minor opcodes are chosen kind of randomly. Why is the funct3 for a left shift given a 1 and a right shift a 5?
@JohnsBasement
3 жыл бұрын
This is a good question. I haven't researched this one yet. It might have to do with an ALU design that can be optimized for reuse in the conditional branch instructions.
@suncrafterspielt9479
3 жыл бұрын
Only one bit differs. It’s actually quite wise
@vinayk.s1674
3 жыл бұрын
hi john, i'm unable to open the website mentioned in the description, it would be helpful if you look in to this issue.
@JohnsBasement
3 жыл бұрын
Try now. I removed the year & semester from the link. BUT now it is for the spring and the RV32I stuff is not yet posted. [I suppose this is one of the downsides of leaving copies of my university lectures on KZitem.] Anything in particular that you are looking for?
@vinayk.s1674
3 жыл бұрын
@@JohnsBasement thanks for the response, I just needed to look in to the website,to get more general information nothing specific
@boralucas8566
2 жыл бұрын
Hi, could you tell me where i can find your pdf book please?
@JohnsBasement
2 жыл бұрын
Click the GitHub link in the video description.
@MarquisDeSang
2 жыл бұрын
39:39 I am only here for this. Without this diagram, it is impossible to understand this mess.
@JohnsBasement
2 жыл бұрын
Grab a copy of the PDF! See the links in the description below the video.
@MarquisDeSang
2 жыл бұрын
@@JohnsBasement Thanks, I just did. I bough myself a Sipeed Nezha Risc-V SBC Linux and I am experiementing with assembly.
@badboi_b23
2 жыл бұрын
is there a link to the pdf?
@JohnsBasement
2 жыл бұрын
In the releases page for the github RVALP project.
@user-lz1yz1rx4x
3 жыл бұрын
thank u sir. can we please get the file u r using in the video!
@JohnsBasement
3 жыл бұрын
RVALP? Look in the video description.
@user-lz1yz1rx4x
3 жыл бұрын
@@JohnsBasement I got it thanks alot
@lamiiia3037
Ай бұрын
hello, in my final exam lecturer asked me that from lw x1 1(x2) where x=1 x=2, what is value of a3 and wd3 also srca and srcb. there was no additional info and i think its impossible to find them without it. and he said you should write but how?
@JohnsBasement
Ай бұрын
I don't understand the notation you are using in this question. x1 and x2 are register names. What does x=1 and x=2 mean? What are srca and srcb?
@lamiiia3037
Ай бұрын
@@JohnsBasement x1 register contains 1 and x2 2. srcA comes from rd1 srcB comes extender. its risc-v single cycle processor
@JohnsBasement
Ай бұрын
@@lamiiia3037 Well, it would depend on the implementation of the CPU. If it does not allow unaligned loads then the instruction would be illegal because it would be reading from x2+1 which would be 3 (not a multiple of 4). If the CPU *does* allow unaligned loads then it would put the 4-byte value read from address 3 into x1. To know the values you'd need to know what is in memory. See also: stackoverflow.com/questions/68245606/risc-v-ram-address-alignment-for-sw-sh-sb
@-blackcat-4749
2 жыл бұрын
That was a 🔐 unexceptional illustration. Just as any other day
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