This was the most general approach i have seen to make clock dividers! this was great!
@TechnicalBytes
3 жыл бұрын
Thanks and glad that you liked this video !!
@armincal9834
3 жыл бұрын
I have been using these frequency dividers in my microcontroller-based projects for almost a year for different purposes but until now I didn't know how it was possible to "divide" a clock frequency, it just makes no sense when you look at it that way, but the picture depicting this "division" actually explained it perfectly, all you do is increase the T by the amount of N you want. I still don't know how these digital blocks actually work but at least I know how they change frequencies
@TechnicalBytes
3 жыл бұрын
🥰🥰🥰🥰🥰
@aakarshithasuresh3096
4 ай бұрын
Thank you for such clear explanation with examples!
@TechnicalBytes
3 ай бұрын
You're very welcome!
@shreyav8453
4 жыл бұрын
seen many videos, but this one actually helped.
@TechnicalBytes
4 жыл бұрын
Thanks for your compliment .. We are going to create a video on clock divider for fractional numbers soon.
@deekeshsahu9257
3 жыл бұрын
In one of the above video you said for delay we have to use dual edge triggered flip flops but in this video u are using either posedge or negedge ff for delay .. why?
@jugal36
5 жыл бұрын
Concepts are very informative and simple to understand...thanks
@TechnicalBytes
5 жыл бұрын
Thanks for your complement..
@vaikh8450
Жыл бұрын
Sir you explained it with such a beautiful manner but please if possible allow the access of your next video.
@TechnicalBytes
Жыл бұрын
Sorry dear, it is our channel policy !!
@ikhwanhaziq7630
3 жыл бұрын
Where is the video for Mod N Counter?
@kollasivaramakrishna6732
2 ай бұрын
great video thank you
@ruslanrahimov5483
3 жыл бұрын
Thank you so much It was very helpful.
@TechnicalBytes
3 жыл бұрын
Very glad to know that this information is helping .. thanks for sharing your views !!
@sahilagarwal8555
4 жыл бұрын
Your channel had amazing informative content. Thanks🙂
@TechnicalBytes
4 жыл бұрын
Glad it was helpful!
@ronakkedia7421
3 жыл бұрын
how negative edge trigger flip flop delays the input by half clock cycle?? Infact it will delay by 1 clock cycle if we are using simple flip-flop
@saiakash6748
2 жыл бұрын
at 11:42nd min how you decided that Q1 columns freq is not f/7? for f/7 counter also could you please add the video of Mod N counter
@Fpg-x2s
3 жыл бұрын
Sir It is fantastic useful clarification like us. Thaks. Gopal raju
@TechnicalBytes
3 жыл бұрын
Thanks and welcome
@udbhavvarma8747
2 жыл бұрын
good video, helped saumya and me!
@TechnicalBytes
Жыл бұрын
Thanks , please keep giving your feedback on other videos as well. your likes and dislikes
@Deepakkumar-tq1xv
4 жыл бұрын
This channel is going to obtain great viewership, I can say that for sure
@TechnicalBytes
4 жыл бұрын
Hope so! Thank you
@shubhamupadhyay5596
4 жыл бұрын
isnt q1 f/7 only? I think it will be tough to make it clock of 50% .....but q1 is periodic
@ecerahuljain
5 жыл бұрын
Very nice explanation
@TechnicalBytes
5 жыл бұрын
Thanks!!!!!
@vini5921
4 жыл бұрын
please make some intersting tricky vede on basic digital electronics
@TechnicalBytes
4 жыл бұрын
Sure .. I have created many .. please go through them as well .. share your valuable feedback also..
@meenugarg1102
5 жыл бұрын
Good way to explain concepts easily
@TechnicalBytes
5 жыл бұрын
Thanks
@meow64912
2 жыл бұрын
thank you bhaiya much appreciated
@TechnicalBytes
Жыл бұрын
Thanks , please keep giving your feedback on other videos as well. your likes and dislikes
@PawanBhakuni
4 жыл бұрын
Beautiful lecture.
@TechnicalBytes
4 жыл бұрын
Glad you liked it
@ammu98
4 жыл бұрын
Sir., Please upload videos on 30% and 70% duty cycle... Thank you so much
@TechnicalBytes
4 жыл бұрын
Please go through the following video: kzitem.info/news/bejne/opx_tH2CnGKIeJw
@vishaljaiswal3736
5 ай бұрын
D flip flop will add 1 clock cycle delay whether its posedge or negedge triggered. Can you please elaborate more how have you generated q2 from q1 in f/3 problem?
@rajatsharma6452
10 күн бұрын
Was fascinated by your simple technique and so excited to check your "fracN" video but you guys put member-only thing there. This is bad man, education should be free.
@neeleshranjan7827
Жыл бұрын
great explanation sir
@TechnicalBytes
Жыл бұрын
Thanks and welcome
@ramireddymaheswari9034
3 жыл бұрын
Hi...very good explanation. I have a question. You were used MOD-N counter in frequency division. As per my knowledge MOD-N counter can implement in synchronous and asynchronous manner also, so which counter it is, synchronous or asynchronous ?
@TechnicalBytes
3 жыл бұрын
In usual practice, synchronous designs are used .. because asynchronous designs are prone to glitches.
@anandkumar-bd2ru
2 жыл бұрын
Synchronous because at the outut of each ff f'= f/n
@dheerajchumble5602
3 жыл бұрын
Excellent tutorial sir....
@TechnicalBytes
3 жыл бұрын
Many many thanks
@mughatoamugha9029
3 жыл бұрын
Sir, what do you mean by q1 is not having a signal f/7? Please explain
@mahalakshmin2394
2 жыл бұрын
As we notice that in mod 7 counter, States are 000 001 010 011 100 101 110 If we take Q1, it's changing from 0 to 1 or 1 to 0 right after 2 clock pulses That is, the frequency of Q1 is f/4
@prashant.yt.99
2 жыл бұрын
hi,negative edge trigger flip flop fwd alters by half cycle, for n/7 example: q2 which is low for 4 cycle will become low for 4.5 cycle ..
@Ash-zw6ch
3 жыл бұрын
Thanks for your effort !
@TechnicalBytes
3 жыл бұрын
My pleasure!
@guybarda7981
4 жыл бұрын
hello, i try by myself to create the f/7 as you shown in the video but there's a problem becase the last falling edge given exsta half clock cycle at '1'. and i am not get 50%. thank you very much for your video!
@TechnicalBytes
4 жыл бұрын
Can you please share your waveform with me??
@joeshannel8021
2 жыл бұрын
@@TechnicalBytes Hi i got the same result , for divide by 7 , if we delay the msb by 0.5 cycle and or it with non delayed version , the final result is -> on period = 4 cycles and off period = 3 cycles and failing to meet 50% duty cycle, could you help here ?
@daanyal3415
Жыл бұрын
Sir, I have a doubt. We are using or gate so it will introduce its own delay practically. So how to we get rid of these issues?Kindly reply sir
@shashikumarbdk7237
3 жыл бұрын
hi sir can you explain frequency multiplier
@tusharkaran6064
2 жыл бұрын
This is a great explanation! Thanks You !!
@TechnicalBytes
Жыл бұрын
You are welcome!
@shahzebimtiaz1849
2 жыл бұрын
Thankyou for the wonderful explanation as always. How would we tackle a situation when the DC produced by the frequency divider is for example say 75% but we want 50% duty cycle? what do we do then? You have addressed the situation where the desired DC is more than the actual DC so we can add flops to achieve that, how do we do it for the example that I mentioned? TIA :)
@faneeshbansal
Жыл бұрын
I am not sure but in that case we can use d flip flop ( negative or positive depending on our requirement) and then will use and gate or some others gates depending on the output we need like xor etc. Thanks
@ashishsingharia2408
3 жыл бұрын
In f/6 why don't we just use q0 to take out the frequency of f/6? then we won't be needing extra hardware for that circuit. Anyone can explain that?
@amradel7920
Жыл бұрын
q0 is a div by 2 it goes like this 010101 but a div by 6 goes like this 000111
@TejSingh-nh1uf
Жыл бұрын
Very nice
@TechnicalBytes
Жыл бұрын
Thanks !!
@rakshitajoshi4430
4 жыл бұрын
Hi...great video! Have a question. Can we generalize the number of flip flops required in any frequency divider? We see that for a f/n divider we need a Mod-n counter which will tell us the number of FFs required according to the bits. But depending upon the number of altering clock cycles, we have to add another FF. So pls suggest if any way to find this.
@TechnicalBytes
4 жыл бұрын
Yes you can! but I am not sure for what purpose, you want to do so .. but let me tell you the answer .. Step1: Just count the number of 0's and 1's in the MSB bit of MOD N counter .. Step2: Get the difference between number of 1's and 0's Step3: divide this difference by 2.. if division is 0, means no flop required. if division is 1, it means 1 posedge flop required. if division is 1.5, it means 1 posedge FF and 1 negedge FF if division is 2, it means 2 posedge FF required. if division is 2.5, it means 2 posedge and 1 Negedge FF ------------------------------------------------------------------------------- -------------------------------------------------------------------------so on.
@anandkumar-bd2ru
2 жыл бұрын
Take n/2 flip flop as we are making johnson counter.
@megfvvd35432
Жыл бұрын
Excellent explanations. How to get access to a video on divide by fractional number. It says to join the channel but no explanation what this means. Thanks
@TechnicalBytes
Жыл бұрын
Actually, some of the videos are not publicly available. Those are available to members only. if you want to become a member, then press on the 'JOIN' button near subscribe button.
@TechnicalBytes
Жыл бұрын
you can press on the following link to join the channel: kzitem.info/rock/niC9ol6QzUH0pVQ3sSfiIQjoin There are two types of memberships, you can join the basic one to get access all the exclusive videos.
@shashikantsingh4993
5 жыл бұрын
sir please upload the video for frequency division by decimal no.. thank you
@TechnicalBytes
5 жыл бұрын
Thanks for showing your interest in our channel..Sure, we will try to make a video of your choice
@TechnicalBytes
4 жыл бұрын
Hello Mr. Shashikant, We have uploaded the requested video. use the following link to access it. kzitem.info/news/bejne/tZ2p34WdpZumjJg
@vikasbansal4180
2 жыл бұрын
Very good explaination
@TechnicalBytes
Жыл бұрын
Thanks !!
@ajaybharti8973
4 жыл бұрын
How can positive edge triggered d flipflop delays the output by 1 cycle...it remains same.
@TechnicalBytes
4 жыл бұрын
Hello Ajay, sorry for the delayed response .. I am sending you a snapshot, Q is missing in it .. Can you please draw it?? I am trying to give you an answer to your question. drive.google.com/file/d/1Os9bVzfb8K_HrcnSjsCCRO4BKxXvHh4k/view?usp=sharing
@TechnicalBytes
4 жыл бұрын
please draw on a notepad, and send it to me..
@snow389
3 жыл бұрын
Hi if we incorporate the value of the CP to Q delay of the added flip flop after the mod N counter, will that still give us the desired result?
@kartiksharma6625
2 жыл бұрын
Please explain how did u created divide by 3 circuit first.
@tze-ven
8 ай бұрын
There is a mistake in you timing diagram of Q3 at 16:30. The pulse for Q3 at the end of the timing diagram is wrongly delayed by half clock cycle instead of 1 full clock cycle.
@hemantrajyora6965
Жыл бұрын
Sir why we can't use q1 input in f/7 frequency divider as it is also a signal of f /7. Any reason for this???
@sanketv1560
4 жыл бұрын
what an amazing explaination !!!!!!!!!!!!!!!!!!!!!
@TechnicalBytes
4 жыл бұрын
Glad to know that you liked this video ..
@farheensultana4627
3 жыл бұрын
Very useful. thank you
@TechnicalBytes
3 жыл бұрын
Glad it was helpful!
@rakshitajoshi4430
4 жыл бұрын
Hi, how can we decide that output Q1 is not a signal with frequency f/7 ?
@TechnicalBytes
4 жыл бұрын
Dear, Q1 is not even a periodic signal .. It is 0 0 1 1 0 0 1 .. It can not be a clock signal. Just repeat this sequence .. 0 0 1 1 0 0 1 . 0 0 1 1 0 0 1 See it is not a clock signal..So, can not take it..
@amandudeja486
Жыл бұрын
The fact that negative edge trig d flop will delay by half cycle is only true if the counter is made of positive edge triggered flip flops. They have to basically be opposite triggering for half cycle delay and same triggering for 1 cycle delay.
@piyushnag6482
10 ай бұрын
i also have same question
@chiyouyu6469
3 жыл бұрын
Excuse me. I have problem. Why we get attention to Q1 in f/5 instead of Q2?
@jkrigelman
Жыл бұрын
How does the f/4 clock divider avoid having a glitch in the center as you transition from counter values 2'b10 -> 2'b11? The others work because the use of the inverted clock being used to create a delayed version that are OR'd together, which helps protect from any potential glitch in the middle.
@anandjj7731
11 ай бұрын
you dont need a mod-n couter for 2^n divisions. f/2 is a single d-ff which has its q' connected back into itself and thus output q serves as an f/2 clock. connect this f/2 clock to the clock input of another d-ff which has its input from it's q' as well. thus the output of d-ff q2 serves as an f/4 clock. you can keep cascading connections to get f/(2^n) divisions.
@gauravkaushal1037
3 жыл бұрын
great video, sir how do i make f/4 with 25% duty cycle?
@sachinbhardwaj6469
Жыл бұрын
Best video 👏🎉 incredibly incredible 😁
@TechnicalBytes
Жыл бұрын
Wow, thanks!
@vadyarshyam4428
Жыл бұрын
for frequency divide by 3 ckt you have taken Q1 and did shifting for the wave generated through d-ff and did or we got output at 3-4.5(On)cycle and 4.5-6(off)cycle. why dont we take Q0 as both have 33.3% duty_cycle? is there any reason taking only Q1?why?
@albertbradfield2311
4 жыл бұрын
For frequency division by integer, couldn't you use a decade counter (4017 for example) and simply take the appropriate output into the reset pin? My mod 7 circuit, which lights the segments of a 7-segment display sequentially, and the dp as the input clock indicator, has the q7 pin (output 8) connected to pin 15 (reset).
@TechnicalBytes
4 жыл бұрын
Thanks for showing your interest in Technical Bytes
@TechnicalBytes
4 жыл бұрын
Sir, you are very correct, we can use Decade counter to divide a frequency but duty cycle will not be 50%. As IC 4071 gives one hot encoded output. It is very easy to convert a one hot counter to clock frequency divider .. Please go through my previous video: kzitem.info/news/bejne/opx_tH2CnGKIeJw
@anjalianand9359
Жыл бұрын
In MOD 7 counter u said we can't use Q1 because it's frequency is not f/7 .. .but why did u use q1 in f/5 counter ...in that case also it doesn't have frequency f/5 ....because only MSB can have f/mod no.
@ashijain2876
3 жыл бұрын
Sir l have one doubt why there is no change in q3 at clock no 5 posedge edge??
@MahiMania7781
3 жыл бұрын
Hi, This video is great. Can you help me to build a frequency divider (f/n; n is odd) with 75% duty cycle?
@bhargava_2003
Жыл бұрын
super sir
@TechnicalBytes
Жыл бұрын
Thanks and welcome!!
@tavicoste8575
Жыл бұрын
8:50 sorry but I can't understand why Q1 is a signal of frequency f/5? Also 11:42 why Q1 is not a signal of f/7? I thought you could optimize the last case by choosing the Q1 column which had 3 high signals and 4 low signals
@shinibalimandal5094
4 жыл бұрын
I have a doubt, how do you get to know that Q1 is not a signal having frequency f/7??
@TechnicalBytes
4 жыл бұрын
Observe Q1 carefully, It is 0 0 1 1 0 0 1 Let us repeat this pattern 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 ........ See Q1 carefully .. It is not even a clock signal .. because logic HIGH and logic LOW times are not fixed .. That is another reason for not considering Q1.. Let me know if you need further clarification..
@sudhajain1081
4 жыл бұрын
@@TechnicalBytes Hi sir, please further clarify the same question.
@sankarjony1237
2 жыл бұрын
Hai sir i want to known about the mod -n counter could u please provide the link, sir please .
@chiragthakur7390
2 жыл бұрын
how to design a circuit with duty cycle of 1/3 using D FF's??
@chandrashekhar6103
5 жыл бұрын
It was a great video. Pls also upload the video of frequency divide by 1.5 counter.
@TechnicalBytes
5 жыл бұрын
Thanks for your complements .. we will try to put requested video on priority
@TechnicalBytes
4 жыл бұрын
Hello Mr. Chandra, We have uploaded the requested video. use the following link to access it. kzitem.info/news/bejne/tZ2p34WdpZumjJg
@captainhades3975
4 жыл бұрын
sir can we use this method for f/16 too?
@TechnicalBytes
4 жыл бұрын
Yes, definitely .. It is simplest, just try once .. if possible, please draw it on page, take a snapshot, store in gdrive and share it here for others ..
@TechnicalBytes
4 жыл бұрын
If you still face issues, then I will share it for you
@shubhamjain8774
Жыл бұрын
@11:48 Q1 is not having frequency which is equal to f/7. So, How to identify which one(Q1,Q2) will have freq f= f/7 .
@yobyag
Жыл бұрын
How can we understand freequncy from truth table?
@prasannapm3220
2 жыл бұрын
best video
@TechnicalBytes
2 жыл бұрын
Thanks !!
@shalinisingh6606
3 жыл бұрын
HOW Q1 IN CASE OF FREQUENCY DIVIDER FOR F/7 IS NOT HAVING FREQUENCY F/N?
@aashnajain6519
3 жыл бұрын
Same doubt
@tanujsharma6316
4 жыл бұрын
How Q1 has same frequency as Q2 in freq/5 case?
@TechnicalBytes
4 жыл бұрын
In f/5 case .. We are using Mod 5 counter which keep on running .. Q1 will be 0 0 1 1 0 As counter keep on running .. so let us repeat this sequence .. 0 0 1 1 0 _ 0 0 1 1 0 _ 0 0 1 1 0 _ 0 0 1 1 0 ........... Just observe this sequence .. it is a train of 2 1's and 3 0's, which means five bits forming a clock. hence it is f/5 Let me know if you need any further clarification.
@_tsitoo_
2 жыл бұрын
silly question but, how would we get the frequency to f/12 using 1 4bit counter (with clear input)?
@98himanshusingh77
Жыл бұрын
take a mod 16 counter ( 4 f/f) clear all fliplops when count reaches 1100. do this using and gate. Qd.Qc.Qb'.Qa' = clear
@omkartrivedi9400
3 жыл бұрын
Cant we design a f/6 using a and gate with q1.q0 and ORing it with q2. ((Q0.Q1)+Q2)
@vasiliynkudryavtsev
2 жыл бұрын
Divide by 6 is very easy divider, because a simple TFF-trigger is enough to divide by 2, next step is by 3 divider (2*3=6), which can be implemented with simple counter. One of the reason of video, I presume, is to make combinational frequency divider, but if divider is multiple of 2 we can do that with synchronous logic.
@ujjwalkumar7199
4 жыл бұрын
Still frequency divider by decimal is not uploaded...u said it is in priority....many other videos came...still waiting for that..🙂😭
@TechnicalBytes
4 жыл бұрын
Sure Ujjwal .. I will do it at priority now ..
@TechnicalBytes
4 жыл бұрын
Hello Mr. Chandra, We have uploaded the requested video. use the following link to access it. kzitem.info/news/bejne/tZ2p34WdpZumjJg
@IITMIAN_ABHILASH
Жыл бұрын
How can we get Q2 waveform here
@hardikjain-brb
3 ай бұрын
8:50 Q1 is not f/5 it is f/4
@rohanmishra5635
4 жыл бұрын
Sir , How to decrease the duty cycle. For example from 50% to 25%.
@TechnicalBytes
4 жыл бұрын
Hello Rohan, Please go through the following video, perhaps it will clarify in more detail: kzitem.info/news/bejne/opx_tH2CnGKIeJw
@TechnicalBytes
4 жыл бұрын
Let me know if it served your purpose..
@sb6701
5 жыл бұрын
I didn’t getting modN counter video link .. can u share here..? I think it’s better to share related links in description than video right corner.
@TechnicalBytes
5 жыл бұрын
Hi, Actually exact MOD N counter video is not created yet .. soon , we will create it and share its link .. And we appreciate your suggestion that we must put corresponding links in the description section.. we will follow it definitely ..
@sb6701
5 жыл бұрын
Technical Bytes thank you 😊
@taptuberay
3 жыл бұрын
@@TechnicalBytes Hi, Is the mod N counter Video ready?
@Sharanya-q2j
Жыл бұрын
@11:26 how can we say that the frequency of bit Q1 is not f/7 ? can you please explain
@sakshisingh4197
3 ай бұрын
Because Q1 is completing it's single cycle in 4 clock pulse not 7 .
@sudhirsingh9265
5 жыл бұрын
Sir please upload video for frequency division by decimal
@TechnicalBytes
5 жыл бұрын
Firstly, thanks for showing your interest in our channel .. we will try to put this video on priority, as many subscribers are requesting..
@TechnicalBytes
4 жыл бұрын
Hello Mr. Sudhir, We have uploaded the requested video. use the following link to access it. kzitem.info/news/bejne/tZ2p34WdpZumjJg
@manveersinghmehra
10 ай бұрын
nice
@TechnicalBytes
10 ай бұрын
Thanks!
@sherlydivyagarikaparthi4187
3 жыл бұрын
can you please upload mod n counter.
@DeepakKumarbidhuri
5 жыл бұрын
just wow great amzing
@TechnicalBytes
5 жыл бұрын
Thanks dear Deepak for your awesome and inspirational words ..
@DeepakKumarbidhuri
5 жыл бұрын
@@TechnicalBytes Sir i want more digital question with tricks pls sir
@TechnicalBytes
5 жыл бұрын
This channel is dedicated to a person like you only.. I am going to put huge material on this channel .. But due to my hectic schedule, i am going bit slow.
@DeepakKumarbidhuri
5 жыл бұрын
@@TechnicalBytes ok sir got it dear if you have some interview as in word or ppt form can u pls send me deepakk.alpine@gmail.com
@DeepakKumarbidhuri
5 жыл бұрын
Dear u dont know u just amazing your questions level n your tricky approach amazing i just love it i believe in realization techniques in digital design
@helpseeker6036
3 жыл бұрын
Can you tell me kindly how can I convert 1 Ghz frequency to 80 Mhz frequency?
@TechnicalBytes
3 жыл бұрын
that means you simply need to divide your input frequency by 12.5.. please refer below mentioned video link to get your answer, let me know if you are able to synthesize your design. kzitem.info/news/bejne/tZ2p34WdpZumjJg
@likhithabandaru8461
Жыл бұрын
I have paid money for membership but I can't able to see videos..
@TechnicalBytes
Жыл бұрын
are you not able to see any of the members video?
@likhithabandaru8461
Жыл бұрын
@@TechnicalBytesNow I can see
@tanishq2195
2 жыл бұрын
Bhai kmap bhi karna hai isme to meri teacher ne number nahi diye kya kar diya ye
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