At 26:35, d_out and t should've been declared as reg variable since they are placed on the left side in an always blocks. showing that this is a behavioral simulation.
@SrikarVarma-jw8hh
3 ай бұрын
in 18:49, explicit association should be " ()", anyone can notice and reply please
@shayokrahmanemon731
Ай бұрын
yes I also notice this and i think you write the correct one
@shashwattripathi5872
3 ай бұрын
in last module "simple_latch", shouldn't 't' be of type 'reg' as it has been assigned inside 'always'?
@ranjanyadav9011
10 ай бұрын
But sir how can at 26:48 the t be modelled as a latch as it is defined as a net data type and you said that net data types can only be modelled as wire??
@guhanrajasekar5993
9 ай бұрын
I think there is a mistake there. I think ' t ' should have been declared as a variable of type ' reg ' .
@DIVITSHARMA-nj9hn
5 ай бұрын
@@guhanrajasekar5993 yes i also feel the same , but it is interesting that no one noticed in 6 yrs!!😲😲
@sakshisingh4197
3 ай бұрын
Oo i noticed after reading this ...that should be reg.
@maradanitejaswi1201
3 ай бұрын
@@sakshisingh4197 Can you explain d_out can't be reg? As it is used on the left side ryt? I believe both t and d_out should be declared as reg.
@arghya.7098
3 ай бұрын
3:53 isn't 1^x = x' (x complement)?
@NikhilMandoli
3 ай бұрын
no.. 1 ^ X= X
@honeygarg2946
17 күн бұрын
yes it should be x'
@arghya.7098
16 күн бұрын
@@honeygarg2946 I think prof is correct. As, x is a state of variable, not a Boolean variable itself.
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