Munsif M. Ahmad
Welcome to our channel, where aspiring VLSI Front-end designers and verification engineers find their ultimate resource for knowledge and growth!
🎓 If you're a student or fresher in the VLSI field, this channel is tailor-made for you! 🎓
Join us on a captivating learning journey focused on two core pillars: Digital Logic Design and Verification. Through an in-depth exploration of fundamental concepts like Verilog HDL, System Verilog HDL as well as HVL, and SV-UVM (Universal Verification Methodology) our main goal is to equip you with the skills and knowledge needed to excel in VLSI Front-end Design & Verification.
🐍 As a bonus, we present pyuvm (python implementation of the UVM using cocotb), where we merge the versatility of Python with the potency of cocotb (COroutine based COsimulation TestBench), revolutionizing the verification ecosystem with innovation and elegance. Witness the fusion of two incredible worlds and expand your horizons beyond traditional boundaries.
- 17:16
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Concept of call-backs w.r.p.t sv-uvm (System Verilog Version of UVM) Part-2 (Modified)
- 12:49
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Concept of memory declaration in RAL w.r.p.t System Verilog Version of UVM -- SV-UVM RAL VIDEO #17
- 16:25
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Example of functional coverage for register w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #16
- 11:47
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reset method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #13
- 9:06
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Update method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #11
- 16:09
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Mirror method w.r.p.t SV-UVM RAL - SV-UVM RAL VIDEO #10
- 15:07
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Concept of an adapter in RAL w.r.p.t System Verilog Version of UVM - SV-UVM RAL VIDEO #05
- 26:08
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Register Abstraction Layer (RAL) SV-UVM RAL VIDEO #04
- 15:15
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Concept of call-backs w.r.p.t sv-uvm
- 5:41
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Array sorting methods w.r.p.t System Verilog
- 13:40
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Can we implement a NOT gate using AND gate?
- 11:41
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Objection mechanism w.r.p.t System Verilog version of UVM
- 4:04
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Design & verification of Protocols using sv-hdl & sv-uvm
- 12:28
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Blocking communication w.r.p.t cocotb
- 15:01
- Жыл бұрын
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