In the lesson Data Transfer between Processing System and Programmable Logic for Zynq / ZynqUS+ SOC by using Vitis HLS is explained. Software test cases on Zynq Ultrascale+ for C Standalone Application (remote processor Cortex R5), Linux C and Python by using Vitis HLS software drivers are demonstrated.
www.fpga-radar.com/axi-dma-hls
0:00 - Introduction
7:57 - Hardware Design with Vitis HLS AXI DMA IP cores
18:46 - Embedded Linux with Buildroot
25:55 - Test case 1: remote processor Cortex R5 standalone C application
36:27 - Test case 2: Linux C application
43:21 - Test case 3: Python application
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Негізгі бет AXI DMA with Vitis HLS
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