Hello Sir ... Very good explanation. 1 small doubt. At 37:00 , you say gmRL /(1+gmRL) =0.9 , But here, gm" is for the NMOS common drain transitor & not bottom NMOS bias transistor, So when Idrain comes to be around 5mA, isnt thats the current flowing through the TOP one & not bottom one "IB"?
@chembiyant456
7 ай бұрын
Hi Suman, you are right. I just watched the video n I did end up saying that. I will make a correction video sometime later. The CD amplifier is driving a resistor n so that will end up deciding the current. The current through the CD amplifier MOS device is Ir+Ibias. So its average current value will be 7+5=12 mA. With 12 mA being the average value, The peak current drawn from supply (and hence the current flowing through the CD MOS device) is 11+5=16 mA (assuming the output swings from 0.3-1.1 V). The minimum current flowing the common drain MOS device is 3+5=8 mA. So the current through the CD MOS device is always greater than 5 mA(it is in fact > 8 mA). Hence the gain will be always greater than 0.9. The current drawn from the supply will be a sinusoidal current oscillating between 16.5 to 8.5 mA, with an average value of 12.5 mA (12+0.5). Assuming 0.5 mA is being spent in the first two stages. So I think that meets all the specs. Plus there is no spec for linearity (THD)., so the gain varying with signal amplitide should not be a problem.
@chembiyant456
7 ай бұрын
Also I assumed that the spec for power given in the problem is average power. If it is peak power then you have decrease the current in the bias device to 1 mA and the CD amplifier device current can go as low as 3+1=4 mA. The gain might go slightly lower than 0.9 V/V at that point. But it can be fixed by increasing the gain of the previous two stages
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