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@saipavanraj961
8 күн бұрын
GOOD EXPLANATION SIR WE NEED MORE VIDEOS ON CDC AND ALSO COME UP WITH LINT
@iswarya01
Жыл бұрын
Very well explained ! Thank you for the video.
@kiranraddimorab3963
2 жыл бұрын
Nicely explained, keep posting concepts related CDC techniques
@Electronicspedia
2 жыл бұрын
Glad you liked. Thanks I will post more videos on other concepts as well. Keep watching, happy learning.
@sourabhjain3346
2 жыл бұрын
Thank you, You are doing a great work
@Electronicspedia
2 жыл бұрын
Thank you 😊
@junedrahi1877
2 жыл бұрын
Thanks, it was explained very nicely. I had a few doubts about this. what if we use a D FF at the source side, and the clk relationship of source and destination is not known as it can change in the later stage of the design. Considering the above constraints 1. for how many clock cycles should the signal be stretched so that it can be sampled at destination clock? 2. Will this technique work or we should go with a handshake-based mechanism?
@Electronicspedia
2 жыл бұрын
If clock relationship is unknown then it's makes sense to go with handshake based mechanism.
@chiraag3972
Жыл бұрын
Nice video - but there might be some inaccuracies at 15:38: While drawing the timing graphs, you are assuming the frequency of clkB matches clkA which is incorrect. doubleq and output of the last flop do not follow clkA frequency -> the pulse at the output of XOR should be as wide as the (timeperiod/2) of clkB. Is that correct?
@Electronicspedia
Жыл бұрын
There is no assumption of clkb freq same as clka. They can be completely asynchronous. Here just got drawing diagram i have considered the clocks same. But the logic still holds good.
@vineethvala3789
2 жыл бұрын
Excellent explanation, can you post more videos on CDC as soon as possible
@Electronicspedia
2 жыл бұрын
Hey thanks for feedback. I have covered basic CDC topics already, please take a look. Will cover more CDC and Reset Domain Crossing (RDC) soon.
@cyrillemagdi7717
2 жыл бұрын
@@Electronicspedia Waiting 🙏
@86sheth
2 жыл бұрын
could you also describe handshaking based circuit for fast to slow
@Electronicspedia
2 жыл бұрын
Hi, I have explained in this video kzitem.info/news/bejne/0nqkvY2maqB4bH4 This is handshake based synchronisation technique
@smitpatel7700
Жыл бұрын
very nice explanation thank you keep it up
@oamkarrama
2 жыл бұрын
Thanks for the explanation
@Electronicspedia
2 жыл бұрын
Thanks for the support. Keep watching Happy learning 👍
@roni5884
2 жыл бұрын
Nicely done Ravi ...carry on
@Electronicspedia
2 жыл бұрын
Thank you 😊
@s.ramtechnical01
Жыл бұрын
sir could you please explain the issue of convergence,divergence and re-convergence with their solutions
@ytaccount9420
7 ай бұрын
For fast to slow, using toggle sync solution, how do we calculate the min cycles to be allowed before we can safely detect next pulse? Is it 4 (toggle ff- 1, double sync -2, d ff -1)? But toggle ff is triggered by clkA, so kinda confused How to calculate safe frequency of pulse
@karanamgururaj6357
Жыл бұрын
I couldn't find the edge detection technique video in your playlist sir could you please share the link if that video
@abdullahjhatial2614
6 ай бұрын
what is difference between two flip flop and std double synchronizer ? they look similar in ciruit
@pavanambala9594
2 жыл бұрын
good one sir
@Electronicspedia
2 жыл бұрын
Thank you 😊
@vinaykumarrhadimani9150
2 жыл бұрын
in the video at fast to slow concept in timing diagram the output of tff is initially zero and when the pulse arrives the output of tff qt should change at the same clock edge as the pulse arrives is that correct?
@Electronicspedia
2 жыл бұрын
Hi Vinay, all the flip flops considered will sampling the signals on the active edge of clocks and these will be sequential elements hence the data will appear on the output in the next clock cycle. But however for waveform representation some people choose to draw it on the same clock.
@vinaykumarrhadimani9150
2 жыл бұрын
@@Electronicspediathankyou so much....
@ItamarEliyahu-v9g
Жыл бұрын
Your Tq is wrong since TFF will also toggle the zero level after the PA pulse to '1' - check it
@BlliondollarX
9 ай бұрын
No its correct, it will detect zero and thats why it will retain past value Qn which is 1 , so tq remains 1. (T flop toggles only if input is 1, if 0 it will retain Qn.
@anilkumarkurra1314
2 жыл бұрын
Hai sir In slow to fast domain after using the dff(after 3rdff) we will generating pulse,but the generated pulse Frequency not same as the pulse frequency of domain A. This is correct??
@Electronicspedia
2 жыл бұрын
Yes you are correct. That is why we call it as clock domain crossing. Crossing of signal/pulse from clock domain A to domain B.
@anilkumarkurra1314
2 жыл бұрын
Thanks for your reply.but in the domain B instead of AND gate (like edge detection) we used XOR.Why can't we use AND gate to generate the pulse instead of xor gate or else shall We use the AND gate?
@Electronicspedia
2 жыл бұрын
XOR gate will generate a pulse in domain B, every time there is a pulse in domain A. Here the thing to be noted is on clock domain A, we are using T flip flop to generate the level signal. That's why we need XOR gate, if you use AND gate based edge detection technique we can detect only either posedge or negedge not both together. But with XOR gate we can detect posedge and negedge both.
@anilkumarkurra1314
2 жыл бұрын
@@Electronicspedia okk Thank you so much for your well explanation.
@Shahidsoc
6 ай бұрын
light is in ur back, so shade come on board
@omegasensors
Жыл бұрын
Sir can u plz share your contact no. Or mail id so that I can send my requirements based on missing pulse detection
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