Electronicspedia
Hey Guys,I am Ravi, working in Semiconductor Industry as Design Engineer. I have done Masters Degree in VLSI Design.
I see a lot of students who are really interested in electronics but however when it comes to a Job they switch to software with the perception that electronics(semiconductor) industry is difficult. I am creating this KZitem channel to teach basics of digital electronics, Verilog coding, Some real world examples and Interview questions that helps you in interviews,
Cheers !!!
Please Like, Share, Comment and Subscribe to my channel for all the updates.
- 10:24
- 2 жыл бұрын
FIFO Depth Calculation | How to Calculate FIFO Depth | Clock Domain crossing | CDC | VLSI Interview
- 7:45
- 2 жыл бұрын
Timescale in Verilog | System Verilog timescale | Compiler Directive `timescale | Verilog Time delay
- 17:24
- 2 жыл бұрын
CDC Methodology | How to Run CDC at SOC level | Clock Domain Crossings | CDC at Subsystem | VLSI
- 13:23
- 2 жыл бұрын
Reset Domain Crossing Technique | RDC Technique | How to fix RDC Violation | VLSI Interview Question
- 7:04
- 2 жыл бұрын
Reset Domain Crossing (RDC) Basics | Reset Recovery | Reset Removal | RDC Basics | VLSI Interview
- 10:16
- 2 жыл бұрын
Verilog Blocking and Non Blocking statements | Blocking Vs Non Blocking | VLSI Interview Question
- 7:44
- 2 жыл бұрын
Clock gating technique in VLSI | Integrated Clock Gating (ICG) | Latch Based Clock Gating |
- 8:09
- 2 жыл бұрын
Clock Gating Basics | Basics of Clock Gating | Clock Gating Techniques |Integrated Clock Gating(ICG)
- 12:05
- 2 жыл бұрын
Synchronous Reset and Asynchronous Reset | Synchronous Reset Vs Asynchronous Reset | What is Reset?
- 20:53
- 2 жыл бұрын
Asynchronous FIFO Design | Async FIFO | Basics of Asynchronous FIFO | Asynchronous FIFO Verilog
- 4:30
- 2 жыл бұрын
Top VLSI Interview Questions | VLSI Interview Questions and Answers | Interview Question and Answer
- 12:01
- 2 жыл бұрын
Synchronous FIFO Design | Basics of Synchronous FIFO | FIFO Full | FIFO Empty Explained
- 25:53
- 2 жыл бұрын
FIFO Clock Domain Crossing (CDC) | FIFO Basics | Asynchronous FIFO | Synchronous FIFO | FIFO Design
- 13:56
- 2 жыл бұрын
Difference Between Latch and Flip Flop | Latch and Flip Flop Difference | VLSI Interview Questions
- 11:31
- 2 жыл бұрын
Reset Synchronizer | Reset Synchronizer Circuit | Active High / Low Reset | VLSI Interview Questions
- 8:57
- 2 жыл бұрын
APB Protocol Basics Read| APB Read Transaction | APB Read Transfer | APB Waveform | APB Protocol
- 12:31
- 2 жыл бұрын
APB Protocol Basics Write | APB Write Transaction | APB Write Transfer | APB waveform | APB Protocol
- 21:30
- 2 жыл бұрын
APB Protocol Basics | APB Protocol Explained | APB Interface | APB Bus Protocol | AMBA APB Topology
- 12:03
- 2 жыл бұрын
Clock Domain Crossing Handshake Synchronizer | CDC Technique | VLSI Interview Question |
- 19:34
- 2 жыл бұрын
Pulse Synchronizer CDC | Toggle Flop synchronization| Fast to Slow Clock| VLSI Interview Question
- 5:47
- 2 жыл бұрын
Edge Detection Circuit | Edge Detection Logic | Positive Edge | Negative Edge | Rising Falling Edge
- 11:14
- 2 жыл бұрын
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