Presentation by Intel recorded at U2U North America 2023.
Presented by TOAI VO
SoC DFT Design Engineer | Intel Corporation
Toai Vo is an SoC DFT design engineer at Intel in San Jose, California where he is responsible for the development of SoC ATPG strategy and methodology. He has more than 30 years of experience in DFT IP design and verification and multi-board/system-level HW/SW co-verification with CPU/emulation. He has designed and implemented Logic BIST solutions in many ASICs. Toai received a BSEE from Portland State University in 1986.
______________________________________________________________________
ABOUT TESSENT SILICON LIFEYCYCLE SOLUTIONS
Tessent Silicon Lifecycle Solutions (formerly Mentor Graphics/UltraSoc) is a division of Siemens EDA (Siemens Digital Industries Software).
Tessent are widely recognized as the industry market leader in delivering design augmentation and linked applications that detect, mitigate and eliminate risks throughout the IC lifecycle. Tessent solutions help customers address their debug, test, yield, safety, security and optimization requirements for today’s most complex SoCs.
Tessent solutions fall into 2 key categories, Tessent Test and Tessent Embedded Analytics.
TESSENT TEST | Design for Test (DFT) and Yield Learning
DFT and yield learning products for logic, memory and mixed-signal devices.
The Tessent Test product suite provides comprehensive silicon test and yield learning applications that addresses the challenges of manufacturing test, debug, and yield ramp.
TESSENT EMBEDDED ANALYTICS | SoC Debug and Analytics
Tessent Embedded Analytics provides solutions for real-time debug and post-deployment analytics for RISC-V-based and other complex SoCs.
_____________________________________________________________________
LEARN MORE
Visit the Tessent website: www. eda.sw.siemens.com/en-US/ic/t...
Email: tessent@siemens.com
#DFTmarketleader
Негізгі бет Ғылым және технология System on Chip ATPG with Tessent Streaming Scan Network (SSN) - INTEL
Пікірлер