Tessent Silicon Lifecycle Solutions
Tessent Silicon Lifecycle Solutions (formerly Mentor Graphics/UltraSoc) is a division of Siemens EDA.Tessent are widely recognized as the industry market leader in delivering design augmentation and linked applications that detect, mitigate and eliminate risks throughout the IC lifecycle. Tessent solutions help customers address their debug, test, yield, safety, security and optimization requirements for today’s most complex SoCs.
Tessent solutions fall into 2 key categories:
TESSENT TEST | Design for Test (DFT) and Yield Learning
DFT and yield learning products for logic, memory and mixed-signal devices.
The Tessent Test product suite provides comprehensive silicon test and yield learning applications that addresses the challenges of manufacturing test, debug, and yield ramp.
TESSENT EMBEDDED ANALYTICS | SoC Debug and Analytics
Tessent Embedded Analytics provides solutions for real-time debug and post-deployment analytics for RISC-V-based and other complex SoCs.
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Tessent Embedded Boundary Scan
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Advances in Shift Left DFT - Nilanjan Mukherjee, Senior Engineering Director, Tessent
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Microsoft | Smart DFT for Complex Semiconductor Designs - Darshan Kobla, Senior Director
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Implementing DFT in 2 5D 3D designs using Tessent Multi die - Lee Harrison at DAC 2023
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Presentation by QUALCOMM - Achieving pattern count reduction through efficient selection and sharing
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Presentation by NXP SEMICONDUCTORS - The road towards In-System Test for automotive ethernet
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Presentation by Intel - Tessent SSN Silicon Bring up
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Targeted screening of bridges with defect oriented tests on automotive designs - NXP Semiconductors
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Break through yield barriers with Siemens and PDF solutions
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Common scan clock generation methods in Tessent SSN (Streaming Scan Network) - TESSENT TEST
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Reducing design for test (DFT) effort with Tessent Streaming Scan Network (SSN) - Dan Trock, Amazon
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The Tessent Streaming Scan network (SSN) - Design for test (DFT) methods for fast time to market
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