Accidentally stumbled on this channel, the title of this video intrigued me. I enojoyed the concept and explanation, it was new to me but more than that, absolutely loved the animations!!
@KarthikVippala
Жыл бұрын
🫡Thank you
@antonymathew
Жыл бұрын
thanks a lot brother.. never seen such a great clarity in explanation for digital design.
@omersarcam3070
7 ай бұрын
Your sense of humor and explanation are very good.
@golinagasandesh4464
Жыл бұрын
Wow!! Great channel for exploring the depths of Verilog
@KarthikVippala
Жыл бұрын
Thank you, brother 🙏
@abhiverma812
11 ай бұрын
Don't use parallel case pragma. Instead use unique decision modifier in front of the case statement. This will ensure that state index is one hot coded. It will give a RT warning in simulation too. Synthesis tool will understand it too.
@KarthikVippala
11 ай бұрын
Yup 😊👍
@tientranmanh798
Жыл бұрын
You should create a video about statemachine using one hot coding. It will bring more value when we use case(1'b1) and enumaration. I love to see your video :D
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