brilliant, i was solving by attaching drain to Vout here also, which is wrong
@aiswaryamohan8158
4 жыл бұрын
Nice lecture , thank you
@semitech01
Жыл бұрын
Thank you. Stay connected for more videos on electronics
@irfankanth368
4 жыл бұрын
Brilliant lecture !
@semitech01
Жыл бұрын
Thank you.
@215_raveenchandra8
3 жыл бұрын
Why for cmos we use capacitor to take the output???? while in bje we generally use a resistor
@semitech01
3 жыл бұрын
If we look at the very purpose of designing any CMOS ....It is nothing but to deliver a clean 0 (logic 0)and clean 1(logic1) at the output , which we can say , is also foundation of a designing a complementary MOS (NMOS+NMOS) which serves the idea of having rail to rail complementary logic which inturn delivers lower power consumption in CMOS as compared to BJT. Capacitor at the output in CMOS helps to store clean 0 and 1 . So serves the purpose of low power consumption in the device which cannot be seen with resistor at the output. On the other hand BJT is preferred in the scenario where high switching speed is required.BJT serves this purpose by having resistance at the output. RC delay is not predominant in BJT due to absence of capacitor at the output. To conclude , I would say one of dominant factor for resistor being at BJT output and capacitor at CMOS is to serve switching speed and rail to rail complementary logic in BJT and CMOS respectively.
@constantkim3155
4 жыл бұрын
thank you for your nice lecture
@semitech01
Жыл бұрын
My pleasure:) stay connected for such videos
@bharatsuthar963830
2 жыл бұрын
Superb concept sir...
@semitech01
Жыл бұрын
Thank you
@princeverma-or7nc
3 жыл бұрын
Thank you sir
@khushalkhan1449
2 жыл бұрын
Great 👍👍👍
@VikasYadav-ju9qv
Жыл бұрын
Nice job
@semitech01
Жыл бұрын
Thank you
@saurabhsharma-ry9cw
Жыл бұрын
Nice one
@semitech01
Жыл бұрын
Thank you:)
@FalakSoomro
5 жыл бұрын
nice
@guttaumasankar8909
4 ай бұрын
I didnt gey why output wont depends on Vt when NMOS connected in Pull down network ?? !!!!!!!
@GateEasy
2 ай бұрын
The output won't depend on Vt because we are considering the NMOS to be ideal, so it acts as a short-circuit path when we apply Vdd as input, and the load capacitor will discharge through the NMOS
@raviiitn7405
2 жыл бұрын
brilliant sir
@semitech01
Жыл бұрын
Thank you
@skireeti5279
4 жыл бұрын
Thank you
@danieltambunan9717
9 ай бұрын
2:35 why do we need to increase Vgs?
@semitech01
9 ай бұрын
In general, Vgs controls the current in the MOSFET . So, with the increase in Vgs current increases and thereby output voltage decreases. But to give a context how we can achieve the maximum output voltage when we consider PMOS as pull down. I said if we increase the Vgs output decreases so we have to decease the Vgs to get higher Vo up to an extent that PMOS stays ON. which is when Vgs=vt . That gives the maximum output of VDD-Vt. Hope it helped !
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